Search results for "Clock rate"
showing 6 items of 6 documents
Extending PluTo for Multiple Devices by Integrating OpenACC
2018
For many years now, processor vendors increased the performance of their devices by adding more cores and wider vectorization units to their CPUs instead of scaling up the processors' clock frequency. Moreover, GPUs became popular for solving problems with even more parallel compute power. To exploit the full potential of modern compute devices, specific codes are necessary which are often coded in a hardware-specific manner. Usually, the codes for CPUs are not usable for GPUs and vice versa. The programming API OpenACC tries to close this gap by enabling one code-base to be suitable and optimized for many devices. Nevertheless, OpenACC is rarely used by `standard programmers' and while dif…
Adapting power consumption to performance requirements in a MSP430 microcontroller
2005
Microcontroller based low power systems using batteries must run at low clock frequencies with short activity periods to extend battery life. These constraints reduce the microcontroller computational capabilities and limit the complexity of algorithms that can be used. New microcontroller architectures, as the Texas Instruments MSP430 family, allow to adapt power consumption to application performance requirements combining several low power modes with the capability of switching the clock frequency dynamically. A complete characterization of power consumption vs. performance has been obtained for the MSP430. A method to determine the range of clock frequencies that meets a consumption and…
FPGA/LST-SW Encryption Module Implementation for Satellite Remote Sensing Secure Systems
2020
The need for security of data transmitted from satellites to the ground has increased. Therefore, the need for secure onboard systems is in great demand, particularly in satellite remote sensing missions. This paper describes an approach for a secure Field Programmable Gate Arrays (FPGA) implementation of the Land Surface Temperature Split Window (LST-SW) algorithm, with objective to meat real-time requirements, area optimization and achieved higher Throughput goals to be sufficient for a secure remote sensing satellite applications and missions. The system is designed using VHDL (VHSIC Hardware Description Language) in a Highlevel design method. The experimental results demonstrate that th…
A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks
2019
New chips for machine learning applications appear, they are tuned for a specific topology, being efficient by using highly parallel designs at the cost of high power or large complex devices. However, the computational demands of deep neural networks require flexible and efficient hardware architectures able to fit different applications, neural network types, number of inputs, outputs, layers, and units in each layer, making the migration from software to hardware easy. This paper describes novel hardware implementing any feedforward neural network (FFNN): multilayer perceptron, autoencoder, and logistic regression. The architecture admits an arbitrary input and output number, units in la…
Performance of the ATLAS silicon strip detector modules
1998
Abstract The performance of the silicon strip detector prototypes developed for use in ATLAS at the LHC is reported. Baseline detector assemblies (“modules”) of 12 cm length were read out with binary electronics at 40 MHz clock speed. For both irradiated and unirradiated modules, the tracking efficiency, noise occupancy, and position resolution were measured as a function of bias voltage, binary hit threshold, and detector rotation angle in a 1.56 T magnetic field. Measurements were also performed at a particle flux comparable to the one expected at the LHC.
Boosting working memory with accelerated clocks
2021
Our perception of time varies with the degree of cognitive engagement in tasks. The perceived passage of time accelerates while working on demanding tasks, whereas time appears to drag during boring situations. Our experiment aimed at investigating whether this relationship is mutual: Can manipulated announcements of elapsed time systematically affect the attentional resources applied to a cognitive task? We measured behavioral performance and the EEG in a whole report working memory paradigm with six items of different colors that each had to be reported after a short delay period. The 32 participants were informed about the current time after each 20 trials, while the clock was running at…